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逻辑仿真

Verilator (Wilson Snyder), under GNU Lesser General Public License v3.0
- A fast free Verilog/SystemVerilog simulator.
Cascade (VMware), under BSD 2-Clause License
- A Just-In-Time Compiler for Verilog from VMware Research.
CVC (Tachyon DA), under Modified Artistic Open Source Software License
- CVC is a full IEEE 1364 2005 compliant Verilog Hardware Description Language (HDL) simulator that compilesVerilog to native X86_64 machine instructions which are executed as a simple native Linux binary.
- Mirror of OSS CVC https://github.com/cambridgehackers/open-src-cvc
OSFPGA GHDL, under GNU General Public License v2.0
- The open-source analyzer, compiler, simulator and (experimental) synthesizer for VHDL.
FreeHDL
- A free, open source, GPL'ed VHDL simulator for Linux.
TkGate, under GNU General Public License v2.0
- A digital circuit editor and simulator with a Tcl/Tk-based interface.
logisim-evolution (a group of Swiss institutes), under GNU General Public License v3.0
- Logisim is an educational tool for designing and simulating digital logic circuits.
DigitalJS (U of Wrocław), under BSD 2-Clause "Simplified" License
- Teaching-focused digital circuit simulator
Icarus Verilog and EpicSim in 标准格式

GTKWave, under GNU General Public License v2.0
- A fully featured GTK+ based wave viewer for Unix and Win32 which reads LXT, LXT2, VZT, FST, and GHW files as well as standard Verilog VCD/EVCD files and allows their viewing.
Ligeia (Lachlan Sneff), under Mozilla Public License 2.0
- A replacement for gtkwave, written in Rust with high-performance and larger-than-memory traces in mind.
WaveDrom, under MIT License
- A Free and Open Source online digital timing diagram (waveform) rendering engine that uses javascript, HTML5 and SVG to convert a WaveJSON input text description into SVG vector graphics.
open-logic-bit, under Apache License v2.0
- Open-source Logic Analyzer gateware for various FPGA dev boards/replacement gateware for commercially available logic analyzers.