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ASIC流程

ASIC Flow

• OpenROAD (UCSD), under various licenses (BSD 2-Clause, BSD 3-Clause, GPL 3.0, ISC, etc.)
  • Aim to develop open-source tools that achieve autonomous, 24-hour layout implementation.
• OpenLANE (efabless), under Apache License 2.0
  • OpenLANE is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen, Fault and custom methodology scripts for design exploration and optimization.
• LibrEDA (Thomas Kramer)
  • The main goal of this project is to create a new libre software framework for the physical design of digital integrated circuits.
• Alliance / Coriolis (Sorbonne Université), under GNU General Public License v2.0
  • Coriolis is a free database, placement tool and routing tool for VLSI designs.
• Chips4Makers
  • The Chips4Makers wants to make it possible for makers and hobbyists to make their own open source chips.
• qflow (Dr. R. Timothy Edwards), under GNU General Public License
  • A Digital Flow using Open Source EDA Tools.
• VSDFLOW (VLSI System Design), "available for download for FREE"
  • An automated RTL-to-GDS flow for programmers, hobbyists, and small-scale entrepreneurs.
• Ophidian (UFSC), under Apache License 2.0
  • An open-source library for physical design research and teaching.
• Rsyn (FURG), under Apache License 2.0
  • An Extensible Physical Synthesis Framework.
• UMpack (UCLA, UMich), under MIT License
  • This release contains over 200,000 lines in C++ implementing industrial-grade VLSI Physical Design tools: the Capo placer, the Parquet floorplanner, the MLPart partitioner, the object-oriented UCLA DB database with LEF/DEF parser and all supporting libraries.
• gEDA, under GNU General Public License v2.0 or later
  • Working on a full GPL'd suite and toolkit of Electronic Design Automation tools.

ASIC Flow Composer

• SiliconCompiler, under Apache License 2.0
  • An open source compiler framework that aims to enable automated translation from source code to silicon.
• Hammer (Berkeley), under BSD 3-Clause License
  • Highly Agile Masks Made Effortlessly from RTL.
• mflowgen (Stanford), under BSD 3-Clause "New" or "Revised" License
  • A modular flow specification and build-system generator for ASIC and FPGA design-space exploration built around sandboxed and modular steps.
• Cocoon (PKU), under BSD 3-Clause "New" or "Revised" License
  • Cocoon is an open-source infrastructure for integrated EDA with interoperability and interactivity.

ASIC Flow (非完全开源)

• DATC Robust Design Flow (IEEE CEDA), under GNU General Public License v3.0
• VLSI CAD Bookshelf 2