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FPGA流程

FPGA Flow

• F4PGA SymbiFlow
  • A Verilog-to-Bitstream (end-to-end) FPGA synthesis flow.
  • Target Xilinx 7-Series, Lattice iCE40 and Lattice ECP5 FPGAs.
• VTR (Toronto), under VTR License
  • A world-wide collaborative effort to provide a open-source framework for conducting FPGA architecture and CAD research and development.
• RAD Flow (U Toronto, Intel)
  • The RAD flow is an open source academic architecture exploration and evaluation flow for novel beyond-FPGA reconfigurable acceleration devices (RADs).
• OSS CAD Suite, under ISC License
  • OSS CAD Suite is a binary software distribution for a number of open source software used in digital logic design.
• IceStorm (Clifford Wolf)
  • Aims at reverse engineering and documenting the bitstream format of Lattice iCE40 FPGAs and providing simple tools for analyzing and creating bitstream files.
  • A working fully open source flow with Yosys and Arachne-pnr.
• FPGA CAD Framework (HES Group at Ghent Univ.)
  • A Java framework focused on rapid prototyping of new CAD algorithms for FPGA compilation.
• hCODE (Kumamoto Univ.)
  • A tool to simplify the creation, sharing, and software integration of FPGA hardware accelerators.
• Automata to Routing (U.Va.)
  • An open-source toolchain to design and evaluate island style spatial automata processing architectures.
• Quicklogic FPGA Toolchain (QuickLogic), under Apache License v2.0
  • SymbiFlow toolchain release packages for Quicklogic FPGAs.

FPGA Flow Composer

• Edalize (Olof Kindgren), under BSD 2-Clause License
  • Edalize is a Python Library for interacting with EDA tools.
• hdlmake (CERN), under GNU General Public License v3.0
  • A tool designed to help FPGA designers to manage and share their HDL code by automatically finding file dependencies, writing synthesis & simulation Makefiles, and fetching IP-Core libraries from remote repositories.
• BFASST (BYU)
  • Tools for FPGA Assurance Flows.
• PyFPGA, under GNU General Public License v3.0
  • PyFPGA is a Python Class for vendor-independent FPGA development.
• DATuner (Cornell, PKU)
  • A parallel bandit-based approach for autotuning FPGA compilation.

FPGA Utilities

• RapidWright (Xilinx)
  • Provide Vivado Interface for users to build customized FPGA implementations.
  • Similar projects: Torc, RapidSmith, and RapidSmith2
• openFPGALoader, under GNU Affero General Public License v3.0
  • Universal utility for programming FPGA.
• reloc (TU Dresden), under MIT License
  • An Open-Sourced Vivado Workflow for Generating Relocatable, Out-Of-Context End-User Configuration Tiles.
• SpyDrNet (BYU), under BSD 3-Clause License
  • A flexible framework for analyzing and transforming netlists. Built to fill an important gap in FPGA research and reliability.
• chisel-vitis-template (CAS ICT)
  • 在Vitis平台上运行Chisel设计.
• Sdaccel-chisel-integration
  • A wrapper in Chisel for using RTL kernels into SDAccel 2017.1.
• Rebit
  • A low level configuration analysis and for the debugging and validation of the bitstream files of architectures that exploit dynamic partial reconfiguration on Xilinx FPGAs.