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开发环境

开发环境

• TerosHDL
  • The goal of TerosHDL is to provide an open source IDE for HDL developers with functionalities commonly used by software developers.
• OSFPGA FOEDAG, under GPL License
  • FOEDAG denotes Qt-based Framework Open EDA Gui.
• OSFPGA VerilogCreator, under GNU General Public License v2.0
  • A QtCreator plugin; it turns QtCreator into a Verilog 2005 IDE.
• Icestudio, under GNU General Public License v2.0
  • Visual editor for open FPGA boards.
• EasySoC CHIP (Xinjun Ma)
  • EasySoC CHIP is an Integrated Development Environment (IDE) and front-end EDA tool for Modern Hardware Design, based on IntelliJ IDEA.
• vtags (Jimmy Situ), under BSD 2-Clause "Simplified" License
  • Verdi like, verilog code signal trace and show hierarchy script.

开发环境 (webware)

• EDA Playground (Doulos)
  • EDA Playground gives engineers immediate hands-on exposure to simulating SystemVerilog, Verilog, VHDL, C++/SystemC, and other HDLs.
• EDA HUB
  • 以数字电路验证为核心目标的EDA平台
• Makerchip (Redwood EDA)
  • A free online environment for developing high-quality integrated circuits.

可视化

• EasySoC Diagrammer (Xinjun Ma), under GNU General Public License v3.0
  • This project can layout and diagram ELK Graph files emitted by layered-firrtl to visualize Chisel generated Firrtl circuits.