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Intermediate Representation (IR)

  • CIRCT, under Apache License
    • "CIRCT" stands for "Circuit IR Compilers and Tools".
  • UHDM, under Apache License 2.0
    • Universal Hardware Data Model (UHDM) is a complete modeling of the IEEE SystemVerilog Object Model with VPI Interface, Elaborator, Serialization, Visitor and Listener.
  • FIRRTL (Berkeley)
    • An intermediate representation (IR) for digital circuits designed as a platform for writing circuit-level transformations.
  • LLHD
    • An intermediate representation for digital circuit descriptions.
    • Together with an accompanying simulator and SystemVerilog/VHDL compiler.
  • Calyx (Cornell), under MIT License
    • An intermediate language and infrastructure for building compilers that generate custom hardware accelerators.
  • LiveHD (UCSC)
    • An infrastructure designed for Live Hardware Development.
    • Including Live Graph (LGraph), Language Neutral AST (LNAST), integrated 3rd-party tools, code generation, and "live" techniques.
  • netlistDB
    • Intermediate format for digital hardware representation with graph database API.
  • nMigen (M-Labs)
    • A refreshed Python toolbox for building complex digital hardware.
  • RTLIL
    • Verilog AST like IR in Yosys.
  • CoreIR
    • An LLVM-style hardware compiler with first class support for generators
  • LLHDL (archived)
    • A logic synthesis and manipulation infrastructure for FPGAs.
  • spydrnet
    • A flexible framework for analyzing and transforming FPGA netlists.
  • fircpp
    • fircpp is a C++ Firrtl parser based on antlr4.
  • SDF3 (Electronic Systems Group), under GNU General Public License and the SDF3 Proprietary License
    • Offers many SDFG transformation and analysis algorithms.