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标准格式

Database

• OpenEDI (NiiCEDA), under BSD 3-clause License
  • An open-source electronic data infrastructure for VLSI design automation.
• OpenDB, under BSD 3-Clause License
  • OpenDB is a design database to support tools for physical chip design.
• LibrEDA DB (Thomas Kramer), under GNU Affero General Public License v3.0
  • LibrEDA DB is a collection of data structures for chip layouts and netlists.

HDL (Verilog, VHDL, etc.)

• SystemVerilog support for Yosys (Antmicro), under Apache License 2.0
  • This repository puts together all the moving parts needed to get SystemVerilog support enabled in Yosys.
• Icarus Verilog (Stephen Williams), under GNU Lesser General Public License v2.1
  • A Verilog simulation and synthesis tool compiling source code written in Verilog (IEEE-1364) into some target format.
• moore (Fabian Schuiki), under dual licensing: Apache License 2.0 or MIT License
  • Moore is a compiler for hardware description languages that outputs llhd assembly, with a focus on usability, clear error reporting, and completeness.
• slang (Michael Popoloski), under MIT License
  • Slang is a software library that provides various components for lexing, parsing, type checking, and elaborating SystemVerilog code.
• Surelog (CHIPS Alliance), under Apache License 2.0
  • SystemVerilog 2017 Pre-processor, Parser, Elaborator, UHDM Compiler. Provides IEEE Design/TB C/C++ VPI and Python AST API.
• sv2v (Zachary Snow), under BSD 3-Clause License
  • sv2v converts SystemVerilog (IEEE 1800-2017) to Verilog (IEEE 1364-2005), with an emphasis on supporting synthesizable language constructs.
• sv-parser, under dual licensing: Apache License 2.0 or MIT License
  • SystemVerilog parser library fully compliant with IEEE 1800-2017.
• tree-sitter-verilog, under MIT License
  • Verilog grammar for tree-sitter.
• verible (Google), under Apache License 2.0
  • Verible is a suite of SystemVerilog developer tools, including a parser, style-linter, and formatter.
• EpicSim (X-EPIC), under GNU Lesser General Public License v2.1
  • A Verilog compiler.
• verilog-parser, a parser for the IEEE 1364-2001 verilog standard
• pyverilog, a hardware design processing toolkit for Verilog HDL including verilog parser, dataflow analyzer, control-flow analyzer and code generator
• verilog (Tom Hawkins), under BSD 3-Clause License
  • A Verilog parser for Haskell.
• hdlparse, a simple package implementing a rudimentary parser for VHDL and Verilog
• NVC, a GPLv3 VHDL compiler and simulator aiming for IEEE 1076-2002 compliance
• GHDL, a VHDL 2008/93/87 simulator
• Related website: Awesome HDL

SystemVerilog support status

• SystemVerilog Tester (SymbiFlow, CHIPS Alliance), under ISC License
  • Test suite designed to check compliance with the SystemVerilog standard.
• UHDM-integration (CHIPS Alliance), under Apache License 2.0
  • Repository for testing SystemVerilog support status in Yosys/Verilator via UHDM

HDL translators

• sv2chisel (OVHcloud), under BSD 3-Clause License
  • sv2chisel translates synthesizable (System)Verilog to low-level Chisel.
• hdlConvertor, under MIT License
  • This library is a System Verilog and VHDL parser, preprocessor and code generator for Python/C++.

LEF/DEF

• Si2 LEF/DEF Toolkit
• RazKarapetyan's LEF/DEF parser
• Tri Minh Cao's LEF parser

Liberty

• Mirror of Synopsys's Liberty parser library

SDC

• Synopsys TAP-in SDC parser
• dalance's SDC parser

GDSII/OASIS

• Gdstk (UNICAMP), under Boost Software License 1.0
  • Gdstk (GDSII Tool Kit) is a C++ library for creation and manipulation of GDSII and OASIS files.
  • It is also available as a Python module meant to be a successor to Gdspy.

Misc.

• Spectre2Spice, under CERN Open Hardware License v2.0 or later
  • A standalone application to translate netlists from the Cadence Spectre Circuit Simulator format to SPICE.