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Network-on-Chip (NoC)

• Constellation (Berkeley), under BSD 3-Clause License
  • Constellation is a Chisel NoC RTL generator framework designed to provide the core interconnect fabric for heterogeneous many-core, many-accelerator SoCs.
• PyOCN (Cornell), under BSD 3-Clause License
  • PyOCN (PyMTL3-net) is a parameterizable and powerful OCN (on-chip network) generator to generate synthesizable Verilog for different OCNs based on user-specified configurations (e.g., network size, topology, number of virtual channels, routing strategy, switching arbitration, etc.).
• OpenSoC Fabric (Lawrence Berkeley National Laboratory)
  • An on-chip network generation infrastructure which aims to provide a parameterizable and powerful on-chip network generator
• OpenSMART (GaTech), under MIT License
  • Single-Cycle Multi-hop NoC Generator in BSV and Chisel.
• NSG (KTH), under BSD 3-Clause License
  • The NoC system Generator is a design flow, which can generate highly configurable NoC-based MPSoC for FPGA instantiation.
• LISNoC (TUM)
  • A free Network-on-Chip implementation, mainly for academic or teaching purposes
• tnoc (Taichi Ishitani), under Apache License 2.0
  • Network on Chip Implementation Written in SystemVerilog.
• NoCRouter (Politecnico di Milano), under MIT License
  • A Network-on-Chip interconnection module with a 2D mesh topology, enabling the connection of computing nodes either in a direct or indirect network.
• nocgen (Keio U)
  • This package includes a Perl script that generates Verilog HDL codes of on-chip network consisting of virtual-channel routers.
• Canal (Stanford)
  • Canal is a DSL that constructs the interconnect through its internal directed-graph representation.

NoC Simulators

• Noxim (Univ. of Catania), under GNU General Public License v2.0
  • A SystemC cycle-accurate Simulator for On-Chip Networks.
• Proteus (GaTech)
  • NoC simulator on FPGA using HLS
• NIRGAM v2.0 (Univ. of Southampton, Malaviya National Institute of Technology), limited to non-commercial educational and research activities
  • A systemC based discrete event, cycle accurate simulator for research in Network on Chip (NoC).
• BookSim 2.0 (Stanford), under BSD 2-Clause License
  • Supports a wide range of topologies such as mesh, torus and flattened butterfly networks, provides diverse routing algorithms and includes numerous options for customizing the network's router microarchitecture.
• ORION 3.0 (UCSD)
  • ORION3.0 fundamental differs from earlier versions of ORION in that the estimation models are derived from actual post P&R layout area and power data that correspond to the actual RTL generator and the actual target cell library.
• HNoCS (Technion)
  • HNOCS is an open-source implementation of a NoC simulation framework using OMNeT++.
• RTL2Booksim (UToronto), under GNU General Public License v2.0
  • This tool allows connecting C/C++ simulators, or RTL (Verilog) designs to Booksim.

Photonic Noc Simulators

• DSENT (MIT)
  • A modeling tool that connects emerging photonics with electronics for opto-electronic networks-on-chip (NoC).

Photonic NoC Mapping Tools

• PhoNoCMap (UniNa), under BSD 3-Clause License
  • An open-source tool for the design space exploration of photonic NoCs mapping solutions.