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单元库

Standard Cell Libraries

• DesignStart Physical IP (ARM)
  • The most comprehensive physical IP with no upfront fees – for companies to produce commercial silicon or for universities to research
• Open-Cell (Si2)
  • Silvaco's 15nm Open-Cell Library
  • No charge for universities and Si2 members
• LibreCell (Thomas Kramer), under GNU General Public License v3.0, CERN Open Hardware Licence v2.0, and GNU Affero General Public License v3.0
  • Aims to be a toolbox for automated synthesis of CMOS logic cells.
• ASTRAN (UFRGS), under BSD 2-Clause "Simplified" License
  • Automatic Synthesis of Transistor Networks (ASTRAN) supports automatic layout generation of CMOS cells from a transistor level netlist description in SPICE format.
• SMT-based-STDCELL-Layout-Generator-for-PROBE2.0 (UCSD), under BSD 3-Clause "New" or "Revised" License
  • SMT-based Simultaneous Place-&-Route for Standard Cell Synthesis for PROBE 2.0.

Hardware Functional Libraries

• Open Logic, under PSI HDL Library License v1.0
  • Open Logic aims to be for HDL projects what what stdlib is for C/C++ projects.
• FPnew (ETH Zürich), under SOLDERPAD HARDWARE LICENSE
  • Parametric floating-point unit with support for standard RISC-V formats and operations as well as transprecision formats, written in SystemVerilog.
• FP-Gen (Stanford), under BSD 3-Clause "New" or "Revised" License
  • A Floating Point Adder/Multiplier/Multiply-Accumulate generator and testbench.
• ArithsGen (Brno University of Technology)
  • ArithsGen presents an open source tool that enables generation of various arithmetic circuits along with the possibility to export them to various representations which all serve their specific purpose.
• FloPoCo
  • A generator of arithmetic cores (Floating-Point Cores, but not only) for FPGAs (but not only).
• GenMul (Univ. of Bremen)
  • GenMul is a multiplier generator which outputs multiplier circuits in Verilog.
• muIR (SFU), under BSD 3-Clause License
  • muIR is a library of hardware components for auto generating highly configurable parallel dataflow accelerator.
• HLSLibs (Mentor)
  • A free and open set of libraries implemented in standard C++ for bit-accurate hardware and software design.
• MatchLib (NVIDIA)
  • MatchLib is a SystemC/C++ library of commonly-used hardware functions and components that can be synthesized by most commercially-available HLS tools into RTL.
• HiFlipVX
  • Open Source High-Level Synthesis FPGA Library for Image Processing.

Configuration and Status Registers (CSR) Generator

• csrGen (Chuck Benz), under Chuck Benz's license
  • csrGen is a tool to automatically build verilog RTL for the CSRs in processor interfaces of many ASIC/FPGA designs.
• RgGen (Taichi Ishitani), under MIT License
  • It will automatically generate soruce code related to configuration and status registers (CSR), e.g. SytemVerilog RTL, UVM register model (UVM RAL), Wiki documents, from human readable register map specifications.
• VGEN (Harvard), under MIT License
  • CHIPKIT currently includes example VGEN scripts for generating CSRs and IO pads, and is easily extensible to other common chip design tasks.