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可重构计算

Fine-grain Reconfigurable Fabrics

• OSFPGA OpenFPGA (UofU), under MIT License
  • An award-winning open-source FPGA IP generator which supports highly-customizable homogeneous FPGA architectures.
• OSFPGA Skywater Opensource FPGAs (SOFA), under MIT License
  • A series of open-source FPGA IPs using the open-source Skywater 130nm PDK and OpenFPGA framework.
• PRGA (Princeton), under BSD 3-Clause License
  • A customizable, scalable, versatile, extensible open-source framework for building and using custom FPGAs.
• FABulous (Manchester), under Apache License 2.0
  • FABulous is designed to fulfill the objectives of ease of use, maximum portability to different process nodes, good control for customization, and delivering good area, power, and performance characteristics of the generated FPGA fabrics.
• Archipelago (Berkeley), under BSD 2-Clause License
  • A parameterizable and user expandable FPGA with toolflow support.
• ZUMA (UBC)
  • Fine Grain FPGA Overlay Architecture and Tools
• literate-broccoli (Will Long)
  • An open source FPGA architecture
  • https://hackaday.io/project/12151-open-source-fpga
• Tritoncore (Jack Davidson)
  • A very simple and minimal FPGA that is implemented in CHISEL
  • Jack Davidson's undergrad project at UCSD

Coarse-grain Reconfigurable Fabrics

• pillars (PKU), under MIT License
  • An open-source CGRA design framework with consistency to assist in design space exploration and hardware optimization of CGRAs.
• TRAM (Fudan), under BSD 3-Clause License
  • Template-based Reconfigurable Architecture Modeling Framework.
• Stream Specialization CGRA Generator (UCLA)
  • As a submodule of dsa-framework, dsa-cgra-gen use JSON to describe CGRA, see example IR in IR directory.
• garnet (Stanford), under BSD 3-Clause License
  • Garnet is a framework to investigate and experiment with implementing CGRA using new generator infrastructure.
  • Magma, under MIT License
    • Magma is a hardware design language embedded in python.
• CGRA-ME (Toronto), under CGRA-ME Software EULA
  • An architectural modelling and exploration (ME) framework
• Mocarabe (Waterloo)
  • The Mocarabe architecture consists of a 2D array of building blocks connected by a directional torus network-on-chip (NoC).
• OpenCGRA2 (Pacific Northwest National Laboratory), under BSD 3-Clause License
  • A parameterizable and powerful CGRA (Coarse-Grained Reconfigurable Architecture) generator to generate synthesizable Verilog for different CGRAs based on user-specified. configurations (e.g., CGRA size, type of the computing units in each tile, communication connection, etc.).
• OpenCGRA (Pacific Northwest National Laboratory), under BSD 3-Clause License
  • A parameterizable and powerful CGRA (Coarse-Grained Reconfigurable Arrays) generator to generate synthesizable Verilog for different CGRAs based on user-specified configurations (e.g., CGRA size, type of the computing units in each tile, communication connection, etc.).
• MDC (UNISS), under BSD 3-Clause License
  • Multi-Dataflow Composer (MDC) design suite.
• SiLago Fabric (KTH), under GNU General Public License v3.0
  • This is the VHDL description of the DRRA and DiMArch CGRA fabric developed by KTH.
  • With manas assembler and vesyla algorithmic synthesis tool.
• UE-CGRA (Cornell)
  • HPCA'21 paper artifact: Analytical performance and energy model (used for both analytical design-space exploration and for the compiler power-mapping pass). A docker image with the CGRA compiler and the RTL source code.

Coarse-grain Reconfigurable Compilers

• SYCL for Vitis 2022.1 (Xilinx), under Apache License v2.0
  • Experimental melting pot with Intel oneAPI DPC++ SYCL and triSYCL for AMD/Xilinx FPGA.
• SODA-OPT (PNNL), under BSD 3-Clause License
  • This project aims to create soda-opt, a tool that leverages mlir to extract, optimize, and translate high-level code snippets into LLVM IR, so that they can be synthesized by our high-level synthesis tool of choice.
• dMazeRunner (ASU), under MIT License
  • dMazeRunner is a framework for automated and efficient search-space and design-space exploration for executing loop kernels on coarse-grained programmable dataflow accelerators.
• CCF (ASU)
  • CCF (CGRA Compilation Framework) is an end-to-end prototype demonstrating the code generation and simulation process for CGRA accelerators.
• CML-CGRA (ASU)
  • SMRA v2.0 (or Software Managed Reconfigurable Accelerator) is initiative of the compiler-microarchitecture lab to boost and promote development of reconfigurable accelerators, containing REGIMap, Instruction Generator/Compiler Backend and Architectural Simulator (gem5).
• CGRAOmp (UTokyo), under MIT License
  • CGRAOmp is a front-end to compile OpenMP codes for Coarse-Grained Reconfigurable Architectures (CGRAs) based on LLVM.