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专用计算

SoC

  • Chipyard (Berkeley), under BSD 3-Clause License
    • An open source framework for agile development of Chisel-based systems-on-chip.
  • Centrifuge (Berkeley), under BSD 3-Clause License
    • A Unified Approach to Generate RISC-V Accelerator SoC.
  • CHIPKIT (Harvard), under MIT License
    • An agile, reusable open-source framework for rapid test chip development.
  • ESP (Columbia), under ESP and Third Party Licenses
    • ESP is an open-source research platform for heterogeneous system-on-chip design that combines a scalable tile-based architecture and a flexible system-level design methodology.
  • LiteX, under BSD 2-Clause License
    • A Migen/MiSoC based Core/SoC builder that provides the infrastructure to easily create Cores/SoCs (with or without CPU).
  • SaxonSoc, under MIT License
    • SoC based on VexRiscv and ICE40 UP5K.
  • Libre-SOC
    • To provide a libre, secure and transparently developed hybrid CPU VPU GPU architecture to the world.
  • OSFPGA FuseSoC (FOSSi), under BSD 2-Clause License
    • An award-winning package manager and a set of build tools for HDL (Hardware Description Language) code.
  • SocLib
    • An open platform for virtual prototyping of multi-processors system on chip (MP-SoC).

DSA

  • DSAGEN (UCLA), under BSD 2-clause License
    • Democratizing Decoupled Spatial Architecture Research.
  • Gemmini (Berkeley), under BSD 3-clause License
    • A systolic-array based matrix multiplication accelerator generator for the investigation of SoC integration of such accelerators.
  • OpenASIP (Tampere University), under GNU Lesser General Public License v2.1
    • OpenASIP (formerly TTA-based Co-design Environment or TCE) is an open application-specific instruction-set toolset. It can be used to design and program customized processors based on the energy efficient Transport Triggered Architecture (TTA).

DNN and Tensor Accelerators

  • AccDNN (IBM, UIUC)
    • A compiler from AI model to RTL (Verilog) accelerator in FPGA hardware with auto design space exploration
  • bnn-fpga (Cornell)
    • An open-source implementation of a binarized neural network (BNN) accelerator for CIFAR-10 on FPGA
  • C-LSTM (PKU, Syracuse)
    • Enabling Efficient LSTM using Structured Compression Techniques on FPGAs.
  • DANA (BU)
    • Dynamically Allocated Neural Network Accelerator for the RISC-V Rocket Microprocessor in Chisel
  • E-LSTM (HKU, PKU)
    • An efficient implementation of LSTM inference on the RISC-V based embedded system
  • FINN (Xilinx), under BSD 3-Clause License
    • Dataflow compiler for QNN inference on FPGAs.
  • FlexCNN (UCLA)
    • An accelerator for running CNNs on FPGA.
  • HLS4ML
    • A package for machine learning inference in FPGAs.
  • MAERI (GaTech)
    • A DNN accelerator with reconfigurable interconnects to support flexible dataflow
  • NEURAghe
    • A flexible and efficient hardware/software solution for the acceleration of CNNs on Zynq SoCs.
  • NVDLA (NVIDIA)
    • A free and open architecture that promotes a standard way to design deep learning inference accelerators
  • PipeCNN (BJTU)
    • An OpenCL-based FPGA Accelerator for Convolutional Neural Networks
  • VTA (UW)
    • A programmable accelerator that exposes a RISC-like programming abstraction to describe compute and memory operations at the tensor level
  • zynqnet (ETH)
    • An FPGA-Accelerated Embedded Convolutional Neural Network

Graphics Processors

Video Processing

  • OpenASIC H.265 Encoder (Fudan)
    • H.265 Video Encoder IP Core 是开源的H.265硬件视频编码器，实现了H.265（或叫HEVC）的大部分功能