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高层综合

High-level Synthesis (HLS)

• hlstool (CIRCT), under Apache License v2.0
  • 'hlstool' composes together a variety of CIRCT libraries that can be used to realise HLS (High Level Synthesis).
  • circt-hls as an inspiration of how tools could be coupled together back in late 2021/early 2022.
• XLS (Google), under Apache License 2.0
  • The XLS (Accelerated HW Synthesis) project aims to enable the rapid development of hardware IP that also runs as efficient host software via "software style" methodology.
• OpenHLS (UChicago), under MIT License
  • This a framework for lowering PyTorch models to RTL using high-level synthesis (HLS) techniques.
• Dynamatic (EPFL), under MIT License
  • Dynamatic is an academic, open-source high-level synthesis compiler that produces synchronous dynamically-scheduled circuits from C/C++ code.
• Intel Compiler for SystemC (Intel), under Apache License v2.0
  • Intel® Compiler for SystemC* (ICSC) translates synthesizable SystemC design to synthesizable SystemVerilog design.
• ScaleHLS (UIUC), under Apache License 2.0
  • ScaleHLS is a next-generation HLS compilation flow, on top of a multi-level compiler infrastructure called MLIR.
• muIR-Generator, a.k.a. Dandelion (SFU), under MIT License
  • muIR-Generator is a tool to generate hardware accelerator from software programs.
• LegUp (Toronto), under LegUp Software End-User License
  • A high-level synthesis tool to improve C to Verilog synthesis without building an infrastructure from scratch.
• PandA (Politecnico di Milano), under GNU General Public License v3.0
  • A usable framework that will enable the research of new ideas in the HW-SW Co-Design field.
• Hastlayer (Lombiq Technologies), under BSD 3-Clause License
  • Hastlayer automatically transforms .NET assemblies into computer chips, improving performance and lowering power consumption for massively parallel applications.
• ROCCC (UC Riverside), under Eclipse Public License 1.0
  • ROCCC (Riverside Optimizing Compiler for Configurable Computing) is a C to VHDL compilation toolset specifically designed for the efficient and rapid generation of high-performance code accelerators on FPGA platforms.
• FCUDA (Advanced Digital Sciences Center), under BSD 3-Clause License
  • A source-to-source transformation framework that takes CUDA kernels with FCUDA annotation pragmas as input and produces a synthesizable C code.
• Shang (Advanced Digital Science Center), under University of Illinois Open Source License
  • An LLVM-based high-level synthesis framework that works on the LLVM machine code layer for easy representation and optimization of some high-level synthesis specific operation (instruction), e.g. reduction OR, concatenation, etc.
• GAUT (Université Bretagne Sud), under CeCILL-B Free Software License
  • A high-level synthesis tool from algorithm to hardware architecture.
• CAPH (INSA Rennes), under Q Public License v1.0 and GNU Library General Public License v2.0
  • CAPH is a domain-specific language for describing and implementing stream-processing applications on reconfigurable hardware, such as FPGAs.
• PipelineC (Julian Kemmerer), under GNU General Public License v3.0
  • A C-like hardware description language (HDL) adding high level synthesis (HLS)-like automatic pipelining as a language construct/compiler feature.
• Centrifuge (Newcastle U), under MIT License
  • Parse GraphML, crunch with Alga, pretty-print to VHDL.

HLS Passes

• EDS Scheduling (SYSU), under MIT License
  • The implementation of Entropy-Directed Scheduling (EDS) algorithm for FPGA high-level synthesis (HLS).
• Polymer (Imperial College London)
  • Bridging polyhedral analysis tools to the MLIR framework.