The Amaranth project provides an open-source toolchain for developing hardware based on synchronous digital logic using the Python programming language, as well as evaluation board definitions, a System on Chip toolkit, and more.
A hardware construction language that supports advanced hardware design using highly parameterized generators and layered domain-specific hardware languages.
HDLGen is a tool for HDL(mainly for Verilog) generation, it enables embedded Perl or Python scripts in Verilog source code, and support Perl style variable anyway, to generate desired HDL in an easy and efficient way.
It wants to add stronger type guarantees and high-level concepts like enums (and structs/typedefs), but also make FPGA design easier and more fun to get involved with.
PyGears is a free framework that lets you design hardware using high-level Python constructs and compile it to synthesizable SystemVerilog or Verilog code.
PyMTL 3 (Mamba) is the latest version of PyMTL, an open-source Python-based hardware generation, simulation, and verification framework with multi-level hardware modeling support.
An open-source domain-specific language (DSL) that enables designers to describe algorithms using a multi-paradigm programming language, and generate the required
Verilog code to implement such systems.
Veriloggen is constructed on Pyverilog. In addition to the low-level abstraction of Verilog HDL, Veriloggen provides high-level abstractions to productively express a hardware structure.
Stream is a dataflow-based high-level synthesis layer for high-performance parallel stream processing.
Thread is a procedural high-level synthesis layer to express sequential behaviors, such as DMA transfers and controls.
A new open-source Domain-Specific Language (DSL) based framework that supports highly abstracted object-oriented hardware defining, programmatical testing, and interactive on-chip debugging.