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逻辑综合

Logic Synthesis

• ALSO (Ningbo Univ.), under MIT License
  • Based on the EPFL Logic Synthesis Libraries; aim to exploit advanced logic synthesis tools for both modern FPGA and emerging nanotechnologies.
• phyLS (Hongyang Pan), under MIT License
  • phyLS is based on the mockturtle and the abc, it can optimize different logics attributes.
• ABC (Berkeley), under a customized license
  • A sequential logic synthesis and formal verification tool.
• OSFPGA EPFL logic synthesis libraries, under MIT License
  • The EPFL logic synthesis libraries are a collection of modular open-source C++ libraries for the development of logic synthesis applications.
  • mockturtle: A logic network library providing several logic network implementations.
  • percy: A header-only exact synthesis library offering a collection of different synthesizers and exact synthesis methods.
  • CirKit: CirKit is a logic synthesis and optimization framework. RevKit 3.1 (for reversible logic synthesis) is a Python library without a stand-alone interface as in CirKit.
• OSFPGA Yosys (Clifford Wolf)
  • A framework for Verilog RTL synthesis, used by qflow and OpenROAD.
• UNIVR Logic Synthesis Software
  • The purpose of this site is to host source code, binaries and documentation of software for combinational and sequential logic synthesis. Currently, the following libraries are made available: Espresso, SIS, MVSIS and BALM.
• QuteRTL (NTU), under GNU General Public License v3.0
  • A RTL Front-End Towards Intelligent Synthesis and Verification.
• FLowGen-CNNs-DAC18 (EPFL), under MIT License
  • Developing Synthesis Flows without Human Knowledge.
• FlowTune (U of Utah)
  • Practical Multi-armed Bandits in Boolean Optimization.
• DRiLLS (Brown U), under BSD 3-Clause License
  • Deep Reinforcement Learning for Logic Synthesis Optimization
• SNS’s not a Synthesizer (SNS) (Duke)
  • predicts the area, power, and timing physical characteristics of a broad range of de- signs at two to three orders of magnitude faster than the Synopsys Design Compiler while providing on average a 0.4998 RRSE (root relative square error)

Approximate Logic Synthesis

• ALSRAC (SJTU)
  • Approximate logic synthesis by resubstitution with approximate care set (DAC'20).
• DALS (SJTU)
  • Delay-driven approximate logic synthesis (ICCAD'18).
• VECBEE (SJTU)
  • Efficient batch statistical error estimation for iterative multi-level approximate logic synthesis (DAC'18).
• Deep-PowerX (USC), free for non-commercial purpose
  • This tool aims at integrating three powerful techniques namely Deep Learning, Approximate Computing, and Low Power Design into a strategy to optimize logic at the synthesis level.
• BLASYS (Brown), under BSD 3-Clause License
  • An Approximate Logic Synthesis Framework based on Boolean Matrix Factorization.