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布局器

Partitioning

  • KaHyPar (Karlsruhe Institute of Technology)
    • A multilevel hypergraph partitioning framework providing direct k-way and recursive bisection based partitioning algorithms.
  • METIS (Univ. of Minnesota)
    • A set of programs for partitioning graphs, partitioning finite element meshes, and producing fill reducing orderings for sparse matrices.

Placer

  • Xplace (CUHK), under BSD 3-Clause License
    • Xplace is a fast and extensible GPU accelerated global placement framework developed by the research team supervised by Prof. Evangeline F. Y. Young at The Chinese University of Hong Kong (CUHK).
  • DREAMPlace (UT Austin), under BSD 3-Clause License
    • A GPU-accelerated analytical placement tool.
  • OpenROAD RePlAce (UCSD)
    • A global placement tool with advancing solution quality and routability validation.
  • OpenROAD OpenDP, integrated in the OpenROAD code repository
    • Open source detailed placement engine.
  • Etesian placer in the Coriolis code repository
    • Coriolis is a free database, placement tool and routing tool for VLSI designs.
  • Capo in the UMpack code repository (UMich)
    • A fast and high-quality routability-driven placer for standard-cell ASICs.
  • qflow Graywolf
    • A placement tool in VLSI design and used together with qflow.
  • RippleFPGA (CUHK)
    • A simultaneous pack-and-place algorithm for FPGA.
  • arachne-pnr
    • A place and route tool for FPGAs.
  • nextpnr
    • A vendor neutral, timing driven, FOSS FPGA place and route tool.

Macro Placer

  • OpenROAD TritonMacroPlacer (UCSD)
    • ParquetFP based macro cell placer for OpenROAD.
  • SMT Macro Placer (Johannes Kepler University Linz), under MIT License
    • Macro Placement for System on Chip design based on solving engines for the Satisfiability Modulo Theories like z3.

Placer (Freeware)

  • ePlace (UCSD)
    • An electrostatics based placer using Nesterov's method.
  • NTUplace (NTU)
    • A ratio partitioning based placer for large-scale mixed-size designs.
  • FastPlace (Iowa State)
    • An Analytical Placer for Large-scale VLSI Circuits.
  • mPL6 (UCLA)
    • Constrained placement by multilevel optimization.
  • Dragon (UCLA)
    • A fast, effective standard-cell placement tool for both variable-die and fixed-die ASIC design.