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动态仿真验证

Verification Framework

• cocotb, under BSD 3-Clause License
  • A coroutine based cosimulation library for writing VHDL and Verilog testbenches in Python.
• pyuvm (Siemens EDA and Ray Salemi), Under Apache License v2.0
  • pyuvm is the Universal Verification Methodology implemented in Python instead of SystemVerilog.
• ChiselVerify (Technical University of Denmark), under BSD 2-Clause License
  • The beginning of a verification library within Scala for digital hardware described in Chisel, but also supporting legacy components in VHDL, Verilog, or SystemVerilog.
• SVAUnit (AMIQ), Apache License v2.0
  • SVAUnit is an UVM compliant package that simplify the creation of stimuli/checkers for validating SystemVerilog Assertions (SVA).

Fuzzing Tools

• rfuzz (Berkeley), under BSD 3-Clause License
  • Coverage-directed fuzzing for RTL research platform.
• RTLFuzzLab (Berkeley), under BSD 2-Clause License
  • RTLFuzzLab is designed to allow for easy experimentation with Coverage Directed Mutational Fuzz Testing on RTL designs.
• hw-fuzzing (UMich, Google, Virginia Tech), under Apache License 2.0
  • To automate test vector generation in an intelligent manner---that boosts coverage---without requiring expensive Design Verification (DV) engineers and tools.

see also Logic Simulation